The glue logic designed in the FPGA reads the serial data from both the inputs using the serial clock and converts the serial data into 64-bit parallel words. A frame sync sequence is detected to determine the start of the input serial data frame. The converted parallel data is buffered on the onboard FIFOs. The size of the FIFO depends on the serial data rate and the latency of the data transfer to the PC. Using DMA transfer the FIFO contents are transferred to the PC RAM. The special software application transfers the data from PC RAM to the PC hard disk. The design ensures no loss of data in the process of transfer from the serial inputs to the storage device.

The glue logic designed in the FPGA reads the serial data from both the inputs using the serial clock and converts the serial data into 64-bit parallel words. A frame sync sequence is detected to determine the start of the input serial data frame. The converted parallel data is buffered on the onboard FIFOs. The size of the FIFO depends on the serial data rate and the latency of the data transfer to the PC. Using DMA transfer the FIFO contents are transferred to the PC RAM. The special software application transfers the data from PC RAM to the PC hard disk. The design ensures no loss of data in the process of transfer from the serial inputs to the storage device.