Parallel Port Based 48 Channel Logic Analyzer (VPL-PPLA-48)

Trigger Setup TimeMore than 20 μsec.
Setup Time4 μsec in internal mode 0 μsec in external mode
Display Timing24 Channel waveform in one screen. The display indicates the time between the cursor 1 and cursor 2.
Hold Time0 μsec in internal mode 8 μsec in external mode
Supply TypeManufacturer, Exporter, Supplier
Preferred Buyer Location All over the world

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Trigger Setup TimeMore than 20 μsec.
Input Impedance1 M Ohm. input capacitor
FilesSave and Load data, Delete and Rename catalog files.
Repeater on TriggerAutomatically starts a new data acquisition cycle after the completion of last cycle and upon detection of trigger word.
Display StateASCII, Binary, Decimal, Hexadecimal in one screen at one time.
Memory Capacity1k data/every channel.
Threshold VoltageTTL (1.4V).
Display Timing24 Channel waveform in one screen. The display indicates the time between the cursor 1 and cursor 2.
Hold Time0 μsec in internal mode 8 μsec in external mode
Frequency50 MHz.
RepeatAutomatically starts a new data acquisition one second after the completion of the previous one.
Trigger Format“0”, “1”. “Xs”.
No. of Channels48
Setup Time4 μsec in internal mode 0 μsec in external mode
Input Voltage+25V transient +10V continuous
PrinterPrint all data on screen to printer
Trigger Position128 to 1920 data before trigger and 1920 to 128 data