Parallel Port Based 48 Channel Logic Analyzer (VPL-PPLA-48)

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Trigger Setup TimeMore than 20 μsec.
Threshold VoltageTTL (1.4V).
Frequency50 MHz.
FilesSave and Load data, Delete and Rename catalog files.
Trigger Format“0”, “1”. “Xs”.
Memory Capacity1k data/every channel.
No. of Channels48
Setup Time4 μsec in internal mode 0 μsec in external mode
Hold Time0 μsec in internal mode 8 μsec in external mode
Trigger Position128 to 1920 data before trigger and 1920 to 128 data
Display StateASCII, Binary, Decimal, Hexadecimal in one screen at one time.
PrinterPrint all data on screen to printer
Input Impedance1 M Ohm. input capacitor
Display Timing24 Channel waveform in one screen. The display indicates the time between the cursor 1 and cursor 2.
RepeatAutomatically starts a new data acquisition one second after the completion of the previous one.
Input Voltage+25V transient +10V continuous
Repeater on TriggerAutomatically starts a new data acquisition cycle after the completion of last cycle and upon detection of trigger word.